NXP Semiconductors
LPC11C12/C14
– C_CAN status
– CANopen object dictionary
– CANopen SDO expedited communication
– CANopen SDO segmented communication primitives
– CANopen SDO fall-back handler
? Flash ISP programming via C_CAN supported.
7.12 10-bit ADC
The LPC11C12/C14 contains one ADC. It is a single 10-bit successive approximation
ADC with eight channels.
7.12.1 Features
?
?
?
?
?
?
?
?
10-bit successive approximation ADC.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 V to V DD .
10-bit conversion time ≥ 2.44 μ s.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or timer match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
7.13 General purpose external event counter/timers
The LPC11C12/C14 includes two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
7.13.1 Features
? A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
? Counter or timer operation.
? One capture channel per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event may also generate an interrupt.
? Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
? Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
LPC11C12_C14_0
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 00.05 — 23 April 2010
? NXP B.V. 2010. All rights reserved.
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